This mini-lesson covers OCR 1.1: what is inside a processor, how it executes an instruction, what genuinely makes it fast, and how data is held when the power goes off.
Work through each screen, answer the questions as you go (some are recall, some are calculations you must actually work out) and collect ⭐ stars. Press Start when you're ready.
The CPU has three parts and a set of tiny, extremely fast stores called registers.
| Register | Job |
|---|---|
| PC — Program Counter | Address of the next instruction |
| MAR — Memory Address Register | The address about to be read from or written to |
| MDR — Memory Data Register | The data or instruction just fetched (or about to be written) |
| CIR — Current Instruction Register | The instruction now being decoded and executed |
| ACC — Accumulator | Holds the results of ALU operations |
Buses: the address bus is unidirectional and its width fixes how much memory can be addressed (n lines → 2ⁿ locations). The data bus is bidirectional and its width fixes how many bits move at once. The control bus carries read, write, clock and interrupt signals.
Interrupts: at the end of each cycle the processor checks the interrupt register. If a higher-priority interrupt is waiting, the current contents of the registers are pushed onto a stack, the appropriate interrupt service routine runs, and the saved state is then popped back so the interrupted program resumes exactly where it left off.
Why the PC is incremented during fetch: so that a branch executed a moment later can simply overwrite it. If the increment came afterwards, every jump would immediately be undone.
The point about cache: a register takes under a nanosecond, cache a few nanoseconds, main memory around 100 nanoseconds. The processor is not waiting on arithmetic — it is waiting on memory. Cache exists to hide that gap, and the hit rate is what decides real-world speed.
| Von Neumann | Harvard |
|---|---|
| One memory for instructions and data | Separate instruction and data memories |
| One shared bus → the von Neumann bottleneck | Separate buses → instruction and data fetched at once |
| Cheap, simple, flexible; general-purpose PCs | Faster and more predictable; embedded systems and DSPs |
| RISC | CISC |
|---|---|
| Few, simple, fixed-length instructions, mostly one cycle | Many, complex, variable-length instructions, several cycles |
| Pipelines beautifully; more registers | Pipelining is hard; fewer registers |
| The compiler does the hard work; more instructions per program | The hardware does it; fewer instructions per program |
| Low power → ARM, in every phone | Historically x86 desktops |
A GPU has thousands of simple cores all executing the same instruction on different data — the SIMD model. That is a perfect match for shading two million pixels, or for the matrix multiplications inside machine learning. Give a GPU a branch-heavy sequential task, however, and it is slower than a CPU.
| Type | How it works | Trade-offs |
|---|---|---|
| Magnetic (HDD) | Magnetised platters, a moving read/write head | Cheap per GB, huge capacity; moving parts, slow seek, fragile |
| Flash / SSD | NAND transistors trapping charge; no moving parts | Fast, silent, shock-proof, low power; dearer; finite write cycles |
| Optical (CD/DVD) | A laser burns pits into a reflective layer | Very cheap, portable, long-lived; slow, small capacity, easily scratched |
Why an SSD feels so much faster: not raw transfer rate, but latency. A hard disk must physically move a head and wait for the platter to rotate — several milliseconds. An SSD addresses any block electronically in microseconds. For thousands of small scattered reads, that is a thousandfold difference.
Tap an item, then tap the group it belongs to.
Tap an item on the left, then its partner on the right.
Processor: ALU · control unit · registers (PC, MAR, MDR, CIR, ACC) · address, data and control buses
FDE: MAR ← PC · PC ← PC + 1 · MDR ← memory · CIR ← MDR · decode · execute; interrupts checked each cycle
Performance: clock speed · cores · cache hit rate · pipelining (flushed by branches) · bus width
Architecture: von Neumann (one memory, bottleneck) vs Harvard (separate, embedded) · RISC vs CISC · GPU = SIMD
Memory: RAM volatile · ROM holds the BIOS · virtual memory pages to disk and can thrash
Storage: magnetic (cheap, moving parts) · flash (fast, finite writes) · optical (cheap, slow, fragile)
That is the whole of OCR 1.1. Press Finish to see your score.
You've worked through Characteristics of processors & devices for OCR A-level Computer Science (H446). 🎉
Your stars: 0 / 0
Next: test yourself in the Evaluate stage Confidence Quiz, then lock it in with Verify.