This mini-lesson covers AQA 4.7 — Fundamentals of computer organisation and architecture: what actually happens inside the processor, instruction by instruction, clock tick by clock tick.
The stored program concept; von Neumann vs Harvard
Registers and buses
The fetch-decode-execute cycle
Factors affecting performance
Addressing modes and assembly language
RISC vs CISC, GPUs and parallel processing
Work through each screen, answer the questions as you go (some are recall, some are calculations you must actually work out) and collect ⭐ stars. Press Start when you're ready.
4.7 · Architecture
The stored program concept
Von Neumann's stored program concept (1945) is the idea the whole industry rests on: instructions and data are stored together in the same memory, in the same binary form, and instructions are fetched and executed one at a time, in sequence.
Before this, a machine was rewired to change its task. Afterwards, you simply loaded a different program. That is what makes a computer general-purpose.
Von Neumann
Harvard
One memory for instructions and data
Separate memories for instructions and data
One set of buses — cheap and simple
Separate buses — instruction and data can be fetched simultaneously
Suffers the von Neumann bottleneck: the single bus is the limiting factor
Faster; memory sizes and word lengths can differ
General-purpose computers
Embedded systems and DSPs, where speed and predictability matter
The bottleneck: the processor can compute far faster than the single shared bus can feed it instructions and data. Cache exists almost entirely to soften this. Modern CPUs are, in truth, hybrids — von Neumann in main memory, Harvard in the split L1 instruction/data cache.
4.7 · The processor
Inside the processor — registers and buses
Components: the ALU (arithmetic and logic), the control unit (decodes instructions and issues control signals), the clock (synchronises everything), and the registers — tiny, extremely fast stores inside the CPU itself.
Register
Job
PC — Program Counter
Holds the address of the next instruction
MAR — Memory Address Register
Holds the address currently being read from or written to
MDR — Memory Data Register
Holds the data or instruction just fetched from (or about to be written to) memory
CIR — Current Instruction Register
Holds the instruction currently being decoded and executed
ACC — Accumulator
Holds the result of ALU calculations
SR — Status Register
Flag bits: Zero, Negative, Carry, Overflow
Buses carry signals between components:
Address bus — unidirectional. Its width sets how much memory can be addressed: n lines → 2ⁿ addressable locations.
Data bus — bidirectional. Its width sets how many bits move at once.
Control bus — carries signals such as read, write, clock, interrupt request.
4.7 · FDE
The fetch-decode-execute cycle
Every instruction the machine has ever run went through this loop:
FETCH
MAR ← PC // address of next instruction
PC ← PC + 1 // increment immediately
MDR ← memory[MAR] // read it over the data bus
CIR ← MDR // hand it to the decoderDECODE
Control unit splits CIR into opcode + operand
EXECUTE
Carry it out (ALU operation, memory access, or branch)
A branch simply overwrites the PC
Why the PC is incremented during fetch, not after: so that a branch instruction executed later can simply overwrite it. If the increment happened after execution, every branch would immediately be undone. This is exactly how an if-statement or a loop works at the metal.
Quick check
The FDE cycle
?During the fetch phase, which register receives the address of the instruction to be retrieved?
4.7 · Performance
What actually makes a processor fast
Clock speed — cycles per second. 3 GHz = 3 × 10⁹ cycles a second. More cycles, more instructions — but only up to the point where heat and the speed of light intervene.
Number of cores — each core executes independently. Two cores are not twice as fast: the gain depends on whether the task can be parallelised, and much software is inherently sequential.
Cache — small, very fast memory holding recently used instructions and data. L1 is smallest and fastest, then L2, then L3. More cache means fewer trips to slow main memory.
Word length and bus width — a wider data bus moves more bits per transfer; a wider address bus reaches more memory.
Pipelining — fetch instruction n+2 while decoding n+1 and executing n. Throughput rises even though each individual instruction takes just as long.
Amdahl's law, in plain English: if 10% of a program cannot be parallelised, then even with infinite cores you can never make it more than 10× faster. The sequential part becomes the whole cost. This is why core counts alone do not save us.
Calculate
Your turn — clock speed
1A single-core processor runs at 2 GHz and completes exactly one instruction per clock cycle. How many instructions does it execute in 5 milliseconds?
instructions
Hint: 2 GHz = 2 × 10⁹ cycles per second. 5 ms = 0.005 s. Multiply.
4.7 · Addressing
Addressing modes and assembly language
The operand of an instruction can be interpreted in different ways. AQA requires two:
Immediate addressing — the operand is the value. Written with a #: MOV R0, #5 puts the literal 5 into R0. Fast, but the value is fixed at compile time.
Direct addressing — the operand is a memory address; the value must be fetched from there. LDR R0, 100 loads whatever is in memory location 100. Slower (an extra memory access), but the value can change at run time.
The AQA assembly instruction set:
LDR Rd, <memory> load from memory into register
STR Rd, <memory> store register into memory
ADD Rd, Rn, <op2> Rd ← Rn + op2
SUB Rd, Rn, <op2> Rd ← Rn - op2
MOV Rd, <op2> copy op2 into Rd
CMP Rn, <op2> compare, set the flags
B <label> branch always
BEQ / BNE / BGT / BLT branch if equal / not equal / greater / less
AND ORR EOR MVN bitwise operations
LSL Rd, Rn, <op2> shift left (each place = × 2)
LSR Rd, Rn, <op2> shift right (each place = ÷ 2)
HALT stop
Calculate
Your turn — trace the assembly
2Trace this AQA assembly program. What value is left in R4?
MOV R0, #5
MOV R1, #3
ADD R2, R0, R1
SUB R3, R2, #2
LSL R4, R3, #2
HALT
Hint: R2 = 5 + 3. R3 = R2 − 2. LSL by 2 places multiplies by 2 twice — that is × 4.
Calculate
Your turn — logical shift right
3Register R1 holds the value 40. The instruction LSR R1, R1, #3 is executed. What does R1 now hold?
Hint: Each place shifted right halves the value. Three places means divide by 2³.
Quick check
Addressing modes
?What is the essential difference between immediate and direct addressing?
4.7 · RISC & parallelism
RISC vs CISC, GPUs and parallel processing
RISC
CISC
Few, simple instructions, each ideally one cycle
Many, complex instructions, taking several cycles
Fixed-length instructions → pipelines beautifully
Variable length → pipelining is hard
More registers; load/store architecture
Fewer registers; instructions can act directly on memory
Complexity pushed into the compiler — more instructions per program
Complexity in the hardware — fewer instructions per program
Lower power → ARM chips in every phone
Historically x86 desktops and servers
Flynn's taxonomy of parallel systems:
SISD — one instruction, one data stream. The classic single-core machine.
SIMD — one instruction applied to many data items at once. GPUs and vector processors live here.
MISD — many instructions, one data stream. Rare; used for fault-tolerant redundancy.
MIMD — many instructions, many data streams. Multi-core CPUs and computer clusters.
Why a GPU beats a CPU at graphics and at machine learning: it has thousands of simple cores executing the same instruction on different pixels or matrix elements — perfect SIMD. Give a GPU a branch-heavy sequential task and it is slower than a CPU. The architecture matches the problem, or it does not.
Quick check
RISC vs CISC
?Why is a RISC architecture well suited to a battery-powered mobile phone?
Quick check
Parallel processing
?A GPU applies the same shading calculation to two million different pixels simultaneously. Which of Flynn's categories is this?
Sort it
Sort the components
Tap an item, then tap the group it belongs to.
📇 Register
🚌 Bus
⚡ Performance factor
Match it
Match the register to its job
Tap an item on the left, then its partner on the right.
Job
Register
Recap
The big ideas to know
Stored program: instructions and data share one memory — this is what makes a computer general-purpose
Architectures: von Neumann = one memory, one bus, a bottleneck · Harvard = separate, faster, used in embedded systems
Registers: PC · MAR · MDR · CIR · ACC · Status Register
Buses: address (unidirectional, 2ⁿ locations) · data (bidirectional) · control
FDE: MAR ← PC · PC ← PC + 1 · MDR ← memory · CIR ← MDR · decode · execute (a branch overwrites the PC)
Performance: clock speed · cores (limited by Amdahl) · cache · bus width · pipelining
Addressing: immediate = the operand is the value (#) · direct = the operand is an address
RISC vs CISC: RISC: few simple single-cycle instructions, pipelines well, low power · Flynn: SISD, SIMD (GPU), MISD, MIMD
That is the whole of AQA 4.7. Press Finish to see your score.
🏆
Mini-lesson complete!
⭐⭐⭐
You've worked through Computer organisation & architecture for AQA A-level Computer Science (7517). 🎉
Your stars: 0 / 0
Next: test yourself in the Evaluate stage Confidence Quiz, then lock it in with Verify.
📣 Smashed it? Share your score
Challenge a mate to beat your stars, or show a parent how you got on.